Method and apparatus for performing N bit by 2*N−1 bit signed multiplications
US6370559B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 1999 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing N bit by 2*N (or 2*N−1) bit signed multiplication using two N bit multiply instructions. According to one aspect of the invention, a method for performing signed multiplication of A times B (where B has N bits and A has N*2 bits) is described. In this method, Ahigh and Alow respectively represent the most and least significant halves of A. According to this method, Alow is logically shifted right by one bit to generate Alow>>1. Then, Alow>>1 is multiplied by B using signed multiplication to generate a first partial result. In addition, a second partial result is generated by performing signed multiplication of Ahigh times B. One or both of the first and second partial results is shifted to align the first and second partial results for addition, and then the addition is performed to generate a final result representing A multiplied by B.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.