Logic flag registers for monitoring processing system events
US6370596B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1999 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Aug 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/86
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of detecting events such as DMA requests, computation operations, configuration set-up operations, occurring in a processing system which are performed by functional system blocks within the system by using logic flags stored in registers within each of the functional system blocks. The registers are coupled to the CPU on dedicated signal lines. Each time a functional block completes an operation or function it updates its corresponding logic flag. The CPU monitors the state of the flags to determine whether certain events have taken place in the system in order to sequentially coordinate functions and operations within the system without the use of interrupt signals on the system bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.