Raid XOR operations to synchronous DRAM using a read buffer and pipelining of synchronous DRAM burst read data
US6370611B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Apr 9, 2002 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory interface controller includes a read buffer to pipeline data from a synchronous dynamic random access memory (DRAM) in response to a plurality of consecutive SDRAM burst read requests, a write buffer to store write data, an exclusive or (XOR) engine to XOR the write data with the data from the read buffer, and a write interface to write resulting data from XORing the write data and the data from the read buffer to the synchronous DRAM. Data is pipelined in the read buffer by repeatedly issuing an SDRAM burst read request before data is transferred out of the synchronous DRAM in response to a previous SDRAM burst read request until a desired amount of data is stored in the read buffer. The memory interface controller thus can perform an external read-modify-write cycle for the synchronous DRAM. The synchronous DRAM can serve as a RAID (Redundant Array s of Inexpensive Disks) memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.