Lateral bipolar junction transistor with reduced parasitic current loss

US6372595B1 · kind B1 · utility

Assignee

• Legerity, Inc. · US

Inventors

• Frank L. Thiel · Sachse, US
• William E. Moore · Macedon, US
• Bruce Webb · Austin, US

Key dates

• Filing date: May 3, 2000
• Grant date: Apr 16, 2002
• Expiry date: May 3, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D10/60

Abstract

A semiconductor process is disclosed which forms openings in a dielectric layer through which the emitter region and collector region of lateral bipolar junction transistors are formed. In one embodiment of the invention, the emitter openings for the lateral bipolar junction transistors are first protected by a photoresist layer that is patterned to expose the collector openings for the transistors. A first implant is performed through the exposed windows in the dielectric layer and into the exposed substrate or epitaxial layer therebelow, and then diffused to a suitable depth. The patterned photoresist is then removed to additionally expose the emitter openings, and a second implant is performed, this time into both the collector and the emitter regions, and then diffused to a suitable depth that is shallower than the first implant (used in the collector). Since the two implants are aligned to openings through the dielectric layer defined typically by a single mask, excellent base-width control and repeatability is achieved for the lateral transistors. Through careful selection of the collector and emitter diffusion profiles (i.e., depth and concentration), a more optimal PNP tran…