Fine pitch bumping with improved device standoff and bump volume
US6372622B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Oct 26, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate generally to solder bump formation and semiconductor device assemblies. One embodiment related to a method for forming a bump structure includes providing a semiconductor device (10) having a bond pad (12), and forming a first masking layer (20) overlying the bond pad (12). The first masking layer (20) is patterned to form a first opening (22) overlying at least a portion of the bond pad (12). A second masking layer (40) is formed overlying the first masking layer (20), and the second masking layer (40) is patterned to form a second opening (42) overlying at least a portion of the first opening (22). The method further includes forming a stud (30) at least within the first opening (22) and a solder bump (60) at least within the second opening (42).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.