Chip scale package with direct attachment of chip to lead frame
US6373125B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Feb 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01079
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip scale package with outer dimensions for high of semiconductor chips to facilitate handling, testing, and later attachment of the package to further electrical circuitry. The chip scale package has four main components: semiconductor chip, a lead frame, a connection between the semiconductor chip and the lead frame, and an encapsulation sealing the semiconductor chip from the surrounding atmosphere. The semiconductor chip has a body, an active surface, and the dimensions that are between about 70% and 80% of the outer dimensions of the chip scale package. The lead frame has an intermediate path directly in line with, and perpendicular to, the surface of the semiconductor chip, thereby minimizing parasitic inductance and capacitance, and a thermal or ground slug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.