Digital receive phase lock loop with residual phase error and cumulative phase error correction
US6373305B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Dec 2, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital PLL's stability and immunity to jitter are improved by deriving the correction to the state machine count from an average over several computations of the phase error, and re-initializing the computation of the phase error to the residual error remaining after the correction. The PLL stability is improved by retaining all of the phase errors measured during a succession of plural phase measurement intervals and by retaining the residual error in the next cycle of cumulative phase error. The plurality of phase errors thus obtained are averaged together starting from the residual error left over from the previous cycle, and the state machine internal count is corrected (updated) in accordance with this average, rather than according to an instantaneous phase error. As a result, the performance of the PLL is less susceptible to jitter-induced temporary excursions in the phase error, a significant advantage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.