Method and apparatus for reducing transistor amplifier hysteresis
US6373331B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Sep 8, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/193
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A biasing method and apparatus which provides bias circuits of radio frequency (RF) power transistors with a low reactive impedance at low frequencies to reduce hysteresis related distortion without affecting the transistor input or output impedance or any impedance matching network which may be used. In one embodiment, reduced hysteresis within a lateral diffused metal-oxide semiconductor (LDMOS) transistor is brought about by a drain bias circuit without any impact on the transistor output impedance. By removing the effect of the bias circuit at RF frequencies, the bias circuit can be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. With a low enough reactive impedance, the hysteresis introduced by the bias circuit is substantially reduced. An auxiliary bias feed external to an RF transistor package is also embodied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.