Digital phase compensation methods and systems for a dual-channel analog-to-digital converter
US6373415B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jan 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06J1/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Phase compensation in a dual-channel analog-to-digital converter (ADC) is accomplished by holding conversion results in programmable length registers for controllable time periods. A dual-channel ADC includes first and second delta-sigma modulators and a digital filter, subject to multiple sampling rates for optimizing coarse and fine adjustments of delay. An energy calculation is performed in a sampled data domain, which is implemented using digital multiplication techniques in a delay compensation scheme performed in the digital domain. The digital data subject to filter processing, is delayed by predetermined amounts. The dual-channel ADC is provided with a programmable channel delay mechanism. A differential delay equal to &Dgr;I-&Dgr;V is calibrated and compensated subject to an acceptable time delay for production of a correct energy value. The ADC according to the present invention further oversamples received analog signal at clock rates much higher than the output rate of the ADC, and delays are generated in the downstream filters connected to the ADC's.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.