Method and apparatus for obtaining linearity in a pipelined analog-to-digital converter
US6373424B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Dec 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/74
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipelined analog-to-digital converter system (10) is responsive to an analog input signal (18). The system includes four pipeline stages (11-14), which each produce a respective digital output (26-29) that is coupled to a combining circuit (16). The combining circuit generates the digital output (41) of the system. Each pipeline stage includes an analog-to-digital converter (101), which generates the digital output for that stage. A shuffler circuit (103) randomly shuffles the bits of this digital output, in order to generate shuffled switching signals, which in turn are used to control electronic switches (206-209, 211-214) associated with several capacitors (C1-C4). By randomly shuffling the switching signals, the effects caused by variation of any capacitor from an ideal value are randomized. This avoids nonlinearity such as harmonic distortion in the analog output signal (21) from that stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.