Semiconductor memory cell and semiconductor memory device
US6373745B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2001 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Mar 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The objective of this invention is to reduce the layout area while guaranteeing data retention stability in a static type semiconductor memory cell. This SRAM cell is constituted with two MOS transistors 10 and 12 and one inverter circuit 14. The source terminal of PMOS transistor 10 is connected to bit line (BL), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to word line (WL). The source tenninal of NMOS transistor 12 is connected to a supply voltage terminal that provides low-level reference potential VSS (for example, zero volts), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to the output terminal o inverter circuit 14. The input terminal of inverter circuit 14 is connected to data storage node (Na).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.