Nonvolatile semiconductor memory having plural data storage portions for a bit line connected to memory cells
US6373746B1 · kind B1 · utility
275Cited by
3References
52Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Sep 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.