Integrated circuit memory devices having control circuits therein that provide column redundancy capability
US6373757B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 17, 2000 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Oct 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Preferred memory devices include a first bit line within a first block of memory and a second bit line within a second block of memory. The first bit line is electrically coupled to a reference voltage signal line by a pull-up transistor that turns on in response to an active first bit line pull-up signal (e.g., /BLPU_IOn=0). The second bit line is also electrically coupled to the reference voltage signal line by a pull-up transistor that turns on in response to an active second bit line pull-up signal (e.g., /BLPU_IOn+1=0). A control circuit is provided and this control circuit is responsive to a multi-bit shift signal. The control circuit disables generation of the active first bit line pull-up signal in favor of an active second bit line pull-up signal when a value of the shift signal designates replacement of the first block of memory with the second block of memory. The control circuit may also generate signals that disconnect a first IO line associated with a defective first block of memory and substitute a second IO line associated with a functional second block of memory for the first IO line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.