Routine testing parity maintenance
US6373819B1 · kind B1 · utility
4Cited by
9References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/241
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for detecting faults in fault detecting hardware designed to detect faults in a data flow comprising a fault generator for deliberately introducing faults in the data flow before it reaches the fault detecting hardware to establish a known background load of faults in the data flow. A fault counter counts actual faults including the deliberately introduced faults. Software analyzes a difference between the known and actual loads of faults.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.