Architecture for a multi-port adapter with a single media access control (MAC)
US6373848B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1998 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jul 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13389
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-port adapter having a single MAC chip has reduced logic circuits for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end to a port multiplexer through an interface and at the other end to respective storage registers. The port multiplexer is coupled to the Physical Layer of each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFO's to write or read data for the selected port. At the end of the cycle, the state registers are set and stay set until selected again. The proc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.