Method of modeling circuit cells with distributed serial loads
US6374203B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1996 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jun 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of serially coupled circuit cells (12-20) are modeled as a distributed serial load. The distributed serial load provides an accurate load model in situations where one cell is effected by loading on subsequent circuit cells, i.e. downstream loading is conveyed back to the first cell. The capacitance (22) and resistance (24, of each cell has a loading effect on each previous cell. The effective resistance and capacitive values of each cell is identified and maintained as one element of the distributed serial load model. The distributed serial load accurately models the loading of unbuffered cells (16-20). The distributed serial load is also applicable to portions of circuit cells (38,40) that are not be buffered and where the downstream loading has an effect on previous circuit drivers (14).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.