Determining error locations using error correction codes
US6374383B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jun 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/158
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A computation circuit for evaluating an error locator polynomial corresponding to a t-error correcting n-symbol code is described. In a first mode of operation, the computation circuit computes r syndromes in response to code word inputs. In a second mode of operation, the computation circuit is provided as inputs the coefficients of the error locator polynomial and evaluates the error locator polynomial for r location values in t+1 clock cycles. For each additional r location values, the inputs are the coefficients multiplied by a finite field element. The power of the finite field element is a multiple s of r. The value of the multiple s is initialized to one. After each next consecutive r location values are computed, sr+r is compared to n−1 and s is incremented prior to computing the next consecutive r location values if sr+1<n−1. If sr+r is ≧n−1, then no further computation of r location values is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.