Method for fabricating semiconductor devices
US6376365B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jun 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor devices having multi-layered wiring structure with an advanced reliability and free from shortcircuit failure between the upper and lower wirings is provided. The method has a step for forming on a first insulating film, having a conductive body exposed thereon, a second insulating film so as to cover the conductive body, and a step for forming by etching a recess to the second insulating film so as to reach the conductive body. In this case at least the lower portion of the second insulating film is formed with a material showing a faster etching rate over at least the upper portion of the first insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.