Low voltage transistors with increased breakdown voltage to substrate

US6376870B1 · kind B1 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• John H. Carpenter, Jr. · Holly Springs, US
• Joseph A. Devore · Dallas, US
• Toru Tanaka · Kumamoto, JP
• Ross E. Teggatz · McKinney, US

Key dates

• Filing date: Sep 8, 2000
• Grant date: Apr 23, 2002
• Expiry date: Sep 8, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/601

Abstract

A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.