Integrated semiconductor chip having leads to one or more external terminals
US6376913B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Aug 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
On the leads of an integrated semiconductor chip which establish a connection to external terminals of a supply voltage, highly clocked current pulses may result in the excitation of potential fluctuations through to resonance oscillations at an internal terminal of the respective lead. In order to attenuate these potential fluctuations, a resistance is prescribed for one or more leads, which resistance is large enough to attenuate the potential fluctuations but is small enough to cause only a predetermined maximum permissible voltage drop on the respective lead. The respective resistance can be obtained by using a material having a corresponding resistivity or by reducing the conductor cross section with a notch along the lead.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.