Position check mark
US6376924B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Jan 18, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.