Composite flag generation for DDR FIFOs
US6377071B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate (i) one or more first enable signals and (ii) one or more first flag signals in response to a first clock signal and a second enable signal. The second circuit may be configured to generate a second flag signal in response to (i) the one or more first enable signals, (ii) the one or more first control signals, (iii) a second clock signal, and (iv) a pulse signal. The third circuit may be configured to generate the pulse signal in response to (i) a third clock signal and (ii) the one or more first flag signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.