Structure and method for reduction of power consumption in integrated circuit logic
US6377073B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0002
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A reduced power dissipation integrated circuit. Power dissipation within a CMOS circuit is reduced by substitution of multi-level buses with several thresholds for binary state buses with a single threshold. A significant portion of an IC's power dissipation is consumed by the act of charging and discharging data and address busses within the IC because theses busses possess the highest capacitances of any of the nodes within the part. The present invention uses a series of thresholds from a minimum voltage to a maximum voltage. Below the minimum threshold voltage Vref1, the logic state would be “0”. Above the maximum threshold voltage Vrefn, the logic state would be “n”. A series of defined thresholds, Vref1, Vref2, . . . Vrefn, between the minimum and maximum voltages define a series of logic states 0, 1, 2 . . . n+1 between 0 and n+1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.