Integrated potentiometer and corresponding fabrication process
US6377115B1 · kind B1 · utility
0Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Oct 4, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/403
Abstract
A process and an integrated circuit are intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by:avalanche of the drain/substrate junction;biasing of the parasitic bipolar transistor of the MOS transistor;irreversible breakdown of the drain/substrate junction; andshorting between the drain and the source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.