Flash memory device
US6377487B1 · kind B1 · utility
10Cited by
1References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 28, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Nov 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device comprises a bank register for selecting the program/erase state of each of the banks, a mode controller for outputting the mode signal of the bank selected by the bank register, an address controller for independently separating an external address into an internal address depending on the output from the bank register, and a plurality of banks for simultaneously performing the program/erase operation and the read-out operation, depending on the mode signal and the internal address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.