Counter register monitor and update circuit for dual-clock system
US6377650B1 · kind B1 · utility
5Cited by
9References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2000 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | Oct 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.