Parallel to serial asynchronous hardware assisted DSP interface
US6378011B1 · kind B1 · utility
11Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Apr 23, 2002 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Parallel data is serialized and transmitted and asynchronous data is received and placed into parallel bytes using a hardware assisted interface. The interface can be driven with very little overhead to the DSP. Additional timing registers and enhanced data buffers decrease the necessary DSP resource commitment. Furthermore the hardware settings in the interface can be adjusted by the DSP to optimize the interface's performance in transmitting various asynchronous protocols.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.