Interposer for chip size package and method for manufacturing the same
US6379159B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Apr 3, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing an interposer for CSP and its intermediate body, a first insulating layer is formed on a cathode substrate. An opening is formed at a position in the insulating layer where a contact is to be formed so that the surface of the substrate is exposed to the inner bottom of the opening. The opening is filled with metal by the electroplating using the cathode substrate as a cathode to form a conductive path. A circuit pattern which is contact with the conductive path is formed on the insulating layer. The cathode substrate is removed partially or entirely so that the end surface of the conductive path is exposed to form a contact. This permits a variation of the heights of a plurality of contacts to be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.