Thin film transistor array substrate for a liquid crystal display
US6380559B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/40
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.