Semiconductor device having FET structure with high breakdown voltage
US6380566B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Nov 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
An N-MOSFET is formed on an SOI substrate consisting of a semiconductor substrate, an insulating layer and an n−-active layer. A p-well layer, an n-RESURF layer, and an n-diffusion layer are formed in the surface of the n−-active layer between a source electrode and a drain electrode by means of impurity diffusion. The diffusion regions of the p-well layer and the n-RESURF layer overlap with each other. An end of the n-RESURF layer reaches a position below a gate electrode. The diffusion regions of the p-well layer and the n-diffusion layer do not overlap with each other, so that the n-RESURF layer has a region in direct contact with the n−-active layer between the p-well layer and the n-diffusion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.