Method to increase coupling ratio of source to floating gate in split-gate flash
US6380583B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Oct 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
Abstract
A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.