Testing integrated circuit dice
US6380729B1 · kind B1 · utility
156Cited by
16References
30Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1305
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing a plurality of integrated circuits. In one embodiment, a plurality of integrated circuits are arranged on a wafer. The integrated circuits are separated on the wafer across the boundary region. Testing interconnects are disposed across the boundary region to test switchable couplings included in each of the integrated circuits on the wafer. After the integrated circuits are tested on the wafer using the testing interconnects across the boundary region, the boundary region is removed, which separates the wafer into individual integrated circuit dice and severs the testing interconnects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.