Semiconductor integrated circuit device, recording medium stored with cell library, and method for designing semiconductor integrated circuit
US6380764B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jun 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor integrated circuit device constructed of MOSFETs in which there is attained a harmony between increase in consumption power due to a leakage current and operating speed of the MOSFETs in a suitable manner, and among a plurality of signal paths in the semiconductor integrated circuit device, a path which has a margin in delay is constructed with MOSFETs each with a high threshold voltage, while a path which has no margin in delay is constructed with MOSFETs each with a low threshold voltage which has a large leakage current but a high operating speed, in light of a delay with which a signal is transmitted along a signal path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.