Reduced lock time for a phase locked loop
US6380810B1 · kind B1 · utility
7Cited by
2References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Aug 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reduced lock time phase locked loop has a speed up circuit with an operational amplifier to amplify a differential voltage across a filter resistor of an RC noise filter, the RC noise filter coupling a coarse tune voltage to a VCO. The amplifed differential voltage is applied to the bases of a pair of opposite polarity transistors, the emitters of the transistors being coupled to a filter capacitor in the RC noise filter for rapid charging/discharging. Alternatively the amplified differential voltage is applied to a pair of parallel, opposite polarity diodes coupled to the filter capacitor for rapid charging/discharging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.