Successive approximation A/D converter capable of error correction
US6380881B2 · kind B2 · utility
16Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2001 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/46
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A successive approximation A/D converter includes a comparator formed of a plurality of comparators and comparing an analog input voltage with a plurality of voltages output from a digital-to-analog converter so as to output a conversion result including at least 2 bits. A control circuit in the A/D converter performs error correction based on the final result output from the comparator and outputs a final conversion result to a conversion result output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.