Semiconductor memory device having variable pitch array
US6381166B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Sep 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell array (300) is disclosed having variable pitch word lines and bit lines. The word lines include central word lines (302a) having a first pitch, and peripheral word lines (302b), situated proximate to the edge of the array (300), having a second pitch that is greater than the first pitch. In a similar fashion, the bit lines include central bit lines (304a) having a third pitch, and peripheral bit lines (304b), situated proximate to the edge of the array (300), having a fourth pitch that is greater than the third pitch. The increase in word line and bit line pitch can reduce the adverse results of proximity effects caused by the junction of the dense array features with the relatively open features of the adjacent periphery circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.