Determining time slot delay for ATM transmission
US6381243B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 1998 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Sep 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5674
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A time slot aligner (60) determines delay (in terms of frames) of time slots of a set of frames received on Plesiochronous Digital Hierarchy (PHD) transmission network. In accordance with the time slot frame/delay determination technique of the invention, the time slot aligner finds an initial header of an ATM cell by searching five consecutive time slots in nearby frames of the set of frames. Once the initial header is found, a frame/delay value is determined for each time slot comprising the header. The frame/delay values for selected time slots of the header are then used to form a window which is used for searching for the next header. Searching for a next header for a next ATM cell involves sliding the window to other frames of the set of frames and searching for a value in a successive time slot which will form a HEC byte for a header framed by the sliding window. When a next header is located, a frame/delay determination has to be made only for the last time slot of the header, e.g., the time slot which formed the HEC byte. A new window is then formed using the frame/delay pattern from the most-recently acquired header, and that new window slid to find yet another header. He…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.