Queued port data controller for microprocessor-based engine control applications
US6381532B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4059
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An engine control system comprising a host processor in operative communication with a data bus and a plurality of peripheral devices for communicating engine operating parameters. Each of the peripheral devices include a first and second transaction register for storing communication parameters for each of the corresponding plurality of peripheral devices. The control system also includes a queued port rate register (QRR) including a memory unit in operative communication with the plurality of peripheral devices for storing data for transmission to the plurality of peripheral devices in accordance with the first and second transaction registers. The system further includes a peripheral counter in operative communication with each of the plurality of peripheral devices. The peripheral counter is adapted to interrogate each of the plurality of peripheral devices and, when data has been written to one of the peripheral devices, update the peripheral device according to the memory unit data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.