System and method for simulating circuits using inline subcircuits
US6381563B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jan 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for generating inline subcircuits that enable a circuit designer to model and simulate circuits that when compared to conventional system and methods reduces the hierarchy from the perspective of the circuit designer, more efficiently models parasitic components, more efficiently parameterizes device models, more effectively creates models that are compatible with other simulation tools, can change the interface of a component without requiring the designer to use an extra layer of hierarchy, provides a more efficient interface by hiding details from the designer, enables hidden monitors and other functional designs to be automatically simulated by hiding these functions from the designer in a design level that is below the design level that is of interest to the designer, such as the geometrical parameter design level, can perform general purpose model binning with automatic selection, can export models and model parameters to other hierarchies without requiring an additional hierarchy in the model name, can allow sharing of exported parameterized models by devices or components that are not within the inline subcircuit definition and can modify or create outpu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.