Method and circuit for controlling a first-in-first-out (FIFO) buffer using a bank of FIFO address registers capturing and saving beginning and ending write-pointer addresses
US6381659B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for controlling a FIFO buffer such that the buffer can accommodate more than one data block simultaneously without overlapping data between adjacent data blocks. The FIFO buffer has a read-pointer address register and a write-pointer address register and a bank of write-capture registers including at least a first pair and a second pair. The first pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a first data block written to the FIFO buffer register while the second pair of registers captures and saves the write-pointer addresses associated with the beginning and ending of a second data block written to the FIFO buffer. The first pair and second pair alternate in capturing and saving beginning and ending addresses of a plurality of data blocks written to the FIFO buffer. In reading data from the FIFO buffer, the read pointer address register is loaded with the previously saved write-pointer address associated with the beginning of each data block that is subsequently read. Since both the beginning and ending write-pointer addresses associated with each data block are captured and saved, the system read…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.