Cache management for a multi-threaded processor
US6381676B2 · kind B2 · utility
75Cited by
8References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 7, 2000 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Dec 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache memory which is allocated to the particular thread from which the access causing the cache miss originated, thereby preventing pollution to partitions belonging to other threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.