System and method for reducing clock skew sensitivity of a shift register
US6381719B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 1998 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Apr 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31725
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The system and method of the present invention for reducing the clock skew sensitivity of a shift register provides a control circuit for generating a clock signal to the first cell of the shift register. The first cell of the shift register receives the clock signal at its input and delays the clock signal for a specified time before transmitting the clock signal to the last cell in the shift register. The clock signal is propagated from the first cell of the shift register to the last cell of the shift register in a first direction. A test data circuit line is coupled to the last cell of the shift register. A test data signal is transmitted by the test data circuit line to the last cell of the shift register and is propagated through the shift register in a second direction, wherein the second direction is in a direction opposite from the direction of the clock signal. Thus, the clock signal is propagated through the cells in the shift register against the flow of the test data signal through the shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.