Method and apparatus for testing high speed input paths
US6381722B1 · kind B1 · utility
8Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1999 |
| Grant date | Apr 30, 2002 |
| Priority date | — |
| Expiry date | Jun 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and circuit to test for defects in the input path of an integrated circuit by providing a logic pattern data to a scan chain of the integrated circuit and testing setup and hold timing parameters. The method including determining a maximum value for a timing parameter and generating a data pattern with the timing parameter having the maximum value. The method also including monitoring an output of a logic function performed on the data pattern and adjusting the value of the timing parameter based on the output of the logic function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.