Patent · US Expired

Method and apparatus for hierarchical restructuring of computer code

US6381739B1 · kind B1 · utility

100Cited by

16References

51Claims

0Family size

Assignee

Motorola, Inc. · US

Inventors

Mauricio Breternitz · Austin, US
Roger Smith · Fuquay-Varina, US

Key dates

Filing date	May 15, 1996
Grant date	Apr 30, 2002
Priority date	—
Expiry date	May 15, 2016

Classification

Technology area (CPC G)Physics
CPC primaryG06F8/443
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A compiler (142) constructs (FIGS. 14-32) a Reduced Flowgraph (RFG) from computer source code (144). The RFG is used to instrument (FIG. 36) code (142). An object module is created (146) and executed (148). Resulting path frequency counts are written to a counts file (154). A compiler (158) uses the source code (144) and the generated counts to identify runtime correlations between successive path edges and Superedges. An object module (159) is generated containing reordered (156) code generated to optimize performance based on the runtime correlations. If cloning is enabled (152), high frequency path edges are cloned (154) or duplicated to minimize cross edge branching.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.