Housing for receiving a planar power transistor
US6384474B1 · kind B1 · utility
2Cited by
3References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Jun 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
With a housing for accommodating a planar power transistor, a chip of the power transistor is arranged hermetically sealed inside the housing, and metallized areas on the chip lead out of the housing by way of electric terminals. At least in some areas, the housing is formed by at least one of the electric power terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.