Buffer circuit
US6384632B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2001 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Feb 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018592
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit comprises a data input terminal; an enabling terminal inputting an enabling signal; an output terminal; a first power source terminal supplying high potential voltage; a second power source terminal supplying low potential voltage; a first N-channel transistor connected between said output terminal and said second power source terminal; a common bulk P-channel transistors group of a first to fifth transistors formed on a common bulk region; a second N-channel transistor formed between said one node and said second power source terminal and comprising a gate electrode supplied an inverted signal of an enabling signal; and a logic circuit either inputting an inverted signal of said input signal to said gate electrodes of said first P-channel transistor and said first N-channel transistor, or inputting a signal keeping said first P-channel transistor turned off to the gate electrode of said first P-channel according to state of said enabling signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.