Signal sampling circuit with high frequency noise immunity and method therefor
US6384641B1 · kind B1 · utility
5Cited by
8References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2001 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Jun 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A signal sampling circuit and method uses a compensating capacitor (30) connected between a ground terminal and an output of an operational amplifier (12) to permit noise error to be applied to both electrodes of a separate output sampling capacitor (18). The noise error component is generated from high frequency noise coupled to the sampling capacitor via a semiconductor substrate. Compensation occurs during a sampling phase and an output operational amplifier (14) is used to filter any high frequency noise during a hold phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.