Temperature and process compensated LDMOS drain-source voltage
US6384643B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Nov 22, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/267
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Driver circuitry (300) is disclosed, incorporating feedback circuitry (310) inter-coupled with reference circuitry (348) to equalize the voltage level of an output (328) with a reference voltage source (320) in the reference circuitry; where the driver circuitry comprises a first transistor (340) having a first terminal coupled to a voltage source (342), a second terminal coupled to an input (336), and a third terminal coupled to a resistor (344), a second transistor (338) having a first terminal coupled to ground (332), a second terminal coupled to an input (334), and a third terminal coupled to a resistor (346), a third transistor (318) having a first terminal coupled to the output, a second terminal (326) coupled jointly to the resistors, and a third terminal coupled to ground, and a resistor (330) coupling the output to a voltage source (306).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.