Serial comparator
US6384713B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2000 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Apr 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In this invention compare circuitry is integrated into a serial shift register which can detect a bit pattern of any length with only the delay of three circuits being added to the shift of the last bit in the bit pattern. The circuitry is connected to operate either is a shift register or as a comparator for an N element bit pattern. Between adjacent registers in the shift register is a MUX used to select compare or shift register operation. An exclusive NOR circuit performs the compare between bits of the serial bit stream and reference bits of the pattern to be protected. An AND circuit accumulates the compare of a particular stage with the compare with the preceding stage. In the last stage the AND circuit provide an accumulated compare result of the preceding number of bit equaling in length the length of the bit pattern for which the compare is being performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.