Clock synchronization circuit and semiconductor device having the same
US6385126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2001 |
| Grant date | May 7, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock synchronization circuit is provided for synchronizing an external clock signal with an internal clock signal. The circuit is connected to a clock buffer adapted to output the internal clock signal. The circuit includes a first loop adapted to receive the external clock signal and output a plurality of reference clock signals having a predetermined phase difference therebetween. A second loop is adapted to delay the plurality of reference clock signals; select a signal from among the plurality of delayed reference clock signals; provide the selected signal to the clock buffer; detect a phase difference between the internal clock signal output from the clock buffer and the external clock signal; generate a plurality of control voltages to reduce the detected phase difference, and control a delay amount of each of the plurality of reference clock signals in response to the plurality of control voltages; so as to synchronize the internal clock signal with the external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.